From the first invention of integrated circuits in 1960, the number of devices on a chip has grown at an explosive increasing rate. The technologies of the semiconductor industry have been researched continuously for almost four decades. The progress of the semiconductor integrated circuits has stepped into the ULSI (ultra large scale integration) level or even higher level. The capacity of a single semiconductor chip has increased from several thousand devices to hundreds of millions of devices, or even to billions of devices. The integrated circuits devices like transistors, capacitors, and connections must be greatly narrowed simultaneously.
The increasing packing density of the integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every device needs to be formed within a smaller size without damaging the characteristics and the operations. The demands on high packing density and low heat generation devices with good reliability and long operation life must be maintained without any degradation in their functions.
All the challenges and demands in fabrication are expected to be solved with the four key aspects of semiconductor manufacturing, including lithography, film formation, etching, and diffusion processing technologies. The continuous increase in the packing density of the integration circuits must be accompanied with a smaller feature size. In addition to chip area and functional considerations, all the devices with smaller size must be achieved with simplified and reliable manufacturing steps to raise the yield and reduce the cost of products.
In the application of memory devices, the SRAM device plays a vital role as a semiconductor storage cell in which the stored data can be latched without degradation. Typically, a SRAM cell is composed of bistable transistor flip-flops which can be implemented in various configurations. MOS (metal oxide semiconductor) transistors or bipolar transistors are used in bistable transistor flip-flops. The SRAM cell utilizes more transistors than a typical DRAM (dynamic random memory) cell which has one transistor and one capacitor. With more transistors employed in forming memory arrays, the packing density of the SRAM array is of great consideration. The packing density must be raised greatly to include more memory cells in a single chip.
The buried contact technology, which utilizes doped poly-crystalline silicon or titanium nitride (TiN) layers for local interconnect, has been widely applied to the modern integrated circuits, such as SRAM and BiCMOS devices. In U.S. Pat. No. 4,701,423 to N. J. Szluk, a totally self-aligned CMOS process is disclosed. It is disclosed that the buried contacts or self-aligned buried contacts are one of the beneficial structures in improving device performance and device density. However, it is difficult to implement the buried contacts with some other beneficial structures like LDD (lightly doped drain), gate/conductor doping, and self-aligned contacts. The process complexity is increased and the device yields is hard to maintain. A CMOS process which incorporates lightly doped drain-source structures, sidewall oxide structures and self-aligned contacts is disclosed.
M. H. El-Downy et al disclose the use of a polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers in U.S. Pat. No. 5,082,796. It is addressed that the number of metal layers formed on a given portion of a wafer is limited. Therefore, the use of a polysilicon layer for local interconnect allows the metal layer that was formerly used for local interconnect to be employed as an additional global connection layer. The use of a polysilicon layer to form device contacts also results in an improvement in transistor performance through a reduction in device parasitic areas.
The buried contacts provide the electrical interconnection among gate electrodes, drain regions of the cross-coupled MOS transistors and source/drain regions of the transmission-gate transistors. However, the typical buried contacts have a major problem in the formation of the buried contact trench which interrupts the transistor current flow path causing device failure.
In U.S. Pat. No. 5,580,806 to T. T. Chang et al, a method of fabricating a buried contact structure for SRAM is disclosed. The buried contacts are used in a MOS SRAM cell, which employs two loads and two cross-coupled MOS transistors to connect each gate electrode to the drain region of the opposing cross-coupled MOS transistors. The trench formation problem in conventional application of the buried contact technology is also illustrated. The resistance is increased under the reduction of the impurity dosage.
Y. H. Wu et al. disclose a trench free process for SRAM in U.S. Pat. No. 5,705,437. The formation of an undoped region or trench is introduced to increase the electrical resistivity or leakage problem. However, the conventional processes in solving the trench formation problem generally incorporate complicated processing steps. The efforts needed in fabrication are thus increased as is the cost. What is needed is a method to form trench-free buried contacts according to a simplified process.